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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//         module EdgeDetector     
//////////////////////////////////////////////////////////////////////////////////
module EdgeDetector # // Parameterizable Edge Detector
(
                // Defines Positive Edge (1) or Negative Edge (0)
    parameter   EDGE = 1
)
(
            // Clock Input
    input   iClk,
            // Asynchronous Reset Input
    input   iRst,
            // Monitored Input Signal
    input   iSignal,
            // Edge Detected Flag
    output  oEdgeDetected
);

//////////////////////////////////////////////////////////////////////////////////
// Internal Signals
//////////////////////////////////////////////////////////////////////////////////
                // Signal Before/After registers Input equation
reg    			rSignal_d;
                // Signal Befor/After registers Output
reg    			rSignal_q;
                // Edge Register Input equation
reg             rEdge_d;
                // Edge Register Output
reg             rEdge_q;
//////////////////////////////////////////////////////////////////////////////////
// Continous assigments
//////////////////////////////////////////////////////////////////////////////////
assign oEdgeDetected = rEdge_q;
//////////////////////////////////////////////////////////////////////////////////
// Sequential logic
//////////////////////////////////////////////////////////////////////////////////
//% Sequential Section<br>
always @(posedge iClk or posedge iRst)
begin
    if(iRst)
    begin
        rSignal_q	<=    1'b0;
        rEdge_q     <=    1'b0;
    end
    else
    begin
        rSignal_q   <=    rSignal_d;
        rEdge_q     <=    rEdge_d;
    end
end
//////////////////////////////////////////////////////////////////////////////////
// Combinational logic
//////////////////////////////////////////////////////////////////////////////////
// Combinational Section
always @*
begin
    // The Before/After register is loaded with present iSignal and the last iSignal
    //value.
    rSignal_d    	=    iSignal;
    if(EDGE)
    begin
        rEdge_d     =   ~rSignal_q & iSignal;
    end
    else
    begin
        rEdge_d     =   rSignal_q & ~iSignal;
    end
end

endmodule
